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Explaning the MSP430G2553
In this post, we will dissect the MSP430G2 package.
What MSP430 has in package?
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications.
Typical applications include low cost sensor systems that capture analog signals, covert them to digital values and then process data for display or for transmission to a host system.
- Interconnect base on Von-Neumann architecture
- 16-bit RISC architecture
- Address/Data bus width: 16-bit
- Memory access range: 16-bit Micro Controller Unit, hence it can address 216 = 64 kB of memory.
- Flexible clock system: The clock system is designed specifically for battery-powered applications.
- Active mode
- Low-power mode 0-4 (LPM0 - LMP4)
Von-Neumann vs Harvard
These two are the basic types of architecture in the microcontroller. but most often Harvard based architecture is mostly prefered.
Below are schemes about fetching data and instructions.
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Von Neumann architecture has a single common memory space where both program instructions and data are stored. It uses same physical pathways for instructions and data.
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Harvard architecture computers have separate memory areas for program instructions and data. It has physically separate pathways for instructions and data.
From the features, it shows that the time for execution of Von-Neumann is high. But the advantage is its simplicity and the cost of hardware is cheaper.
Peripherals
- Oscillator and System Clock
- Main DCO Characteristics
- GPIO
- Watchdog Timer
- Timer
- Comparator
- ADC10
- I2C
- SPI
- UART
MSP430 Memory Organization
- 16-bit memory address bus (MAB) allows direct access and branching throughout entire memory range.
- 16-bit memory data bus (MDB) allows direct manipulation of word-wide arguments.
- Direct memory-to-memory transfers without intermediate register holding.
- 16-bit addresses, addressing to bytes
- Aligned words: The address of a word is the address of the byte with the lower address, which must be even.
- Little-endian ordering: The low-order byte is stored at the lower address and high-order byte at higher address.